A semiconductor imaging chip is an integrated circuit containing a two dimensional array of photosensitive diodes and amplifiers known as “active pixel sensors” (APS). A “pixel” is a single picture element, such as one dot of a given color. The imaging chip is placed in the focal plane of a digital camera and exposed to an image during the camera shutter time interval. Diodes in the silicon substrate detect the light, and generate electrons, which accumulate negative charge on n-type junctions in the semiconductor circuit substrate.
Initially, each photodiode is reset to an initial positive voltage. A focused image is projected onto the surface of the chip. Incident light discharges the initial positive voltage on each photodiode by an amount proportional to the total light flux. The time between reset and readout is the image exposure time or shutter time interval. A mechanical shutter is simulated by resetting a given photodiode, and then reading out the voltage on the photodiode a short time later.
The photodiode array is arranged in rows and columns. The resulting voltage on each of the photodiodes is read out by means of scanning and signal processing circuits, which are typically included on the imaging chip. Individual APS cells are addressed by accessing each row of the APS cell array individually and sensing the respective outputs of the corresponding APS cells in the selected row on the plurality of columns in the array. A column buffer is provided for each column.
Pattern Noise in the APS Cell Array
Each APS cell contains a photodiode and a small amplifier formed by field effect transistors (FET) operated as a source follower (a current amplifier) circuit. A suitable active pixel sensor containing a photodiode and four transistors forming a source follower amplifier circuit is disclosed in U.S. Pat. No. 4,445,117 to Gaalema et al. The disclosed APS cell includes a first control line to access the photodiode during readout, and a second separate control line to reset the photodiode after readout in preparation for the next image exposure. An improved APS cell layout with merged access and control lines is disclosed in U.S. Pat. No. 5,083,016 to Wyles et al.
Pattern noise results from the small differences between individual FET transistors in each APS cell. In particular, each source follower buffer in each APS cell will have a (different) offset voltage between the photodiode voltage and the output column bus voltage, which offset voltage is equal to about one gate-to-source threshold of the FET source follower transistor. Since there are random variations of the offset voltage between individual FET transistors on the order of some tens of millivolts, the random offset voltages produce a fixed pattern of noise arising from the imaging chip itself, which pattern noise will be superimposed on the imaged illumination. The pattern noise caused by the variation in APS offset voltage is unacceptably large for most applications, and particularly in the case of low power cmos semiconductor fabrication.
Pattern Noise Cancellation
Pattern noise is cancelled in the column buffers that readout the image data stored in the APS cells. To cancel pattern noise the APS pixel signal value is readout and sampled. The APS cell is reset and the APS reset signal value is sampled. The difference between the sampled (stored) APS pixel signal value and the measured offset voltage in the reset condition (the stored APS reset signal value) is proportional to the true pixel (photodiode) illumination. By taking the difference between the previously stored sampled APS pixel signal value and the current APS reset signal value, an output pixel signal value is produced in which the source follower buffer offsets are cancelled. In other words, by subtracting the reset signal value of the current APS cell from the pixel signal value of the current APS cell, the pattern noise due to the source follower offset is cancelled.
Column Buffer Layout on a Semiconductor Chip
In a semiconductor chip, circuits are constructed at or near the surface of a silicon wafer. A column buffer circuit contains memory elements and amplifiers. A first memory element stores the current APS pixel signal value and a second memory element stores the current APS reset signal value. A first (differential gain) amplifier is responsive to the stored current APS pixel signal and stored APS reset signal values to subtract one stored signal from the other and provide a corrected APS pixel signal value output. Corrected APS pixel signal value outputs are further stored in odd and even row memory elements. A second (bus driver) amplifier is provided, responsive to the stored corrected APS pixel signal values stored in the odd and even row memory elements, in order to drive the output bus from the photodiode array.
A semiconductor imaging chip needs many photodiodes in order to provide suitably detailed images. To increase the photographic detail (i.e., obtain more resolution by having more pixels), the number of photodiodes in the array is typically increased, which increases the number of columns. However, increasing the number of photodiodes in the same size array results in more closely spaced columns, leaving less room for each column buffer. As a result, each column buffer in a larger photodiode array must be laid out in an area resembling a very long and narrow corridor. The awkward area available results in inefficient layout and ultimately limits the maximum potential size of the imaging array.